1. The Field of the Invention
The present invention relates generally to a programmable array logic circuit macrocell using ferromagnetic memory cells. More particularly, the present invention uses a non-volatile ferromagnetic memory cell to temporarily store binary data.
2. The Background Art
Programmable logic devices have any number product sets, usually in groups of four (4), eight (8), sixteen (16) or more bits, although often in groups of ten (10). The arrays are programmed for application-specific tasks to be performed within digital electronic circuits. The fusible link types cannot be re-programmed, but those employing EEPROM and Flash can. For those PALs which use fusible links, the data in the xe2x80x9cDxe2x80x9d registers is lost at power off. For those that use EEPROM and Flash as replacements for the xe2x80x9cDxe2x80x9d registers, data is not lost at power off time.
Up to the present, traditional PALs have used xe2x80x9cDxe2x80x9d type flip-flops for product registers. Lately, however, some fabricators have begun using EEPROM and Flash technology to replace these. These last two technologies have drawbacks, however. EEPROMs are cumbersome to re-program, both are slow to re-program, exhibit xe2x80x9cwrite fatigue,xe2x80x9d thereby limiting their useful life, and must be mass-written to re-program.
It has been recognized that it would be advantageous to develop a programmable array logic circuit macrocell using ferromagnetic memory cells. More particularly, the present invention uses a non-volatile ferromagnetic memory cell to temporarily store binary data.
It is an advantage of the invention to have the ferromagnetic memory cells or bits to store data even when there is no power provided to the circuitry, thus saving power during operation of the programmable logic circuitry, and ensuring that there is no loss of the data should there be a temporary power shut down.
Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein, thus eliminating xe2x80x9cwrite fatiguexe2x80x9d.
The invention provides an integrated circuit, comprising a programmable OR array, a programmable AND array, coupled to the programmable OR array, and a macrocell output circuit. The macrocell uniquely has a ferromagnetic bit and sensor coupled to store a remnant output signal, and an output buffer, coupled to output the remnant output signal upon receiving a output enable signal. The macrocell may further include a DQ register that contains the ferromagnetic bit. The DQ register may also include a drive coil, which at least partially surrounds the ferromagnetic bit. Drive coils may have a bi-directional current that sets the polarity of the ferromagnetic bit. The bi-directional current may be switched by two sets of transistor pairs. The two sets of transistor pairs may, in turn, be gated by first and second transistor respectively. The first and second transistors may be responsive to a DATA signal that is received when a CLOCK signal is received.
Additional features and advantages of the invention will be set forth in the detailed description which follows, taken in conjunction with the accompanying drawing, which together illustrate by way of example, the features of the invention.